1. Field of the Invention
The present invention relates to integrated circuits, the operation of which may be disturbed by an ionizing radiation.
2. Discussion of the Related Art
FIG. 1 is a cross-section view of an N-channel MOS transistor (NMOS) and of a P-channel MOS transistor (PMOS) of a portion of a SRAM-type memory comprised within an integrated circuit. The integrated circuit is formed in and above a lightly-doped P-type substrate 1. An N-type well 2 is formed in the upper portion of substrate 1. In the present description, “well” will be used to designate a relatively thick upper substrate area or portion at the surface of which MOS transistor drain/source areas may be formed. In this example, two drain/source areas 3 and 4 are placed at the surface of N well 2. A heavily-doped N-type well contact area 5 is placed at the surface of N well 2. Drain/source areas 6 and 7 are placed at the surface of substrate 1. A heavily-doped P-type substrate contact area 8 is placed at the surface of substrate 1. Drain/source areas 3/4 and 6/7 are separated by channel areas above which are placed insulated gates 10 and 11.
This memory portion exhibits a set of parasitic components which are not disturbing in a standard use of the memory but which may become so when a radiation reaches the substrate at the level of this cell. A set of charged particles is then created along the path of the radiation in substrate 1, and/or well 2. Such a set of charges then generates parasitic currents likely to trigger a latch-up phenomenon, which is described hereafter.
Source area 4, N well 2, and substrate 1 form a first parasitic PNP bipolar transistor T1. Source area 7, substrate 1, and N well 2 form a second parasitic NPN bipolar transistor T2. Further, N well 2 is equivalent to a resistor R1 between well contact area 5 and the base of parasitic transistor T1. Similarly, P substrate 1 is equivalent to a resistor R2 between substrate contact area 8 and the base of parasitic transistor T2.
FIG. 2 is an equivalent electric diagram of the parasitic circuit formed by the above-mentioned parasitic components. In a standard memory use, source area 4 and well contact area 5 are connected to a supply voltage Vdd. Source area 7 of the NMOS transistor and substrate contact area 8 are connected to ground GND. The emitter of transistor T1, corresponding to source area 4, and resistor R1 are then connected to supply voltage Vdd. The emitter of transistor T2, corresponding to source area 7, and resistor R2 are grounded. Resistor R1 is placed between the emitter and the base of transistor T1. Resistor R2 is placed between the ground and the base of transistor T2. The collector of transistor T1 is connected to the base of transistor T2. Similarly, the collector of transistor T2 is connected to the base of transistor T1.
When a radiation reaches the substrate, a parasitic current ip creates through resistor R2 and, accordingly, a voltage V2 creates across resistor R2. Voltage V2 is applied between the base and the emitter of transistor T2. Voltage V2 can be sufficient to turn on transistor T2. A current i2 then crosses transistor T2 and resistor R1 and a voltage V1 creates across resistor R1. Voltage V1 is applied between the base and the emitter of transistor T1. When voltage V1 is sufficient, bipolar transistor T1 turns on. A current i1 then crosses transistor T1 and resistor R2. The system is then “latched up” since each transistor generates the current necessary to turn on the other transistor. The occurrence of this parasitic thyristor latch-up or turn-on phenomenon results in creating a very lightly resistive conduction path between supply voltage Vdd and ground GND.
Known means for avoiding the above-described latch-up phenomenon comprise modifying the structure of the memory cell such as shown in FIG. 1. However, such solutions result in increasing the circuit size, which goes against an ever-increasing integration of the number of components on a given integrated circuit surface area.
Further, technological solutions enable decreasing the probability of occurrence of the latch-up phenomenon but do not totally suppress the risk of having a short-circuit between the supply voltage and the ground, such a short-circuit causing not only a significant consumption but also operation errors of the integrated circuit.